DDFT control
DDFT_OUT0_SEL | Select signal for CPUSS DDFT[0] 0: clk_r of the Main flash (which is clk_hf for SONOS Flash) 1: Flash data output bit ‘0’ (r_q[0]) 2: Flash data output bit ‘32’ (r_q[32]) 3: Flash data output bit ‘64’ (r_q[64]) 4: Flash data output bit ‘127’ (r_q[127]) 5: bist_fm_enabled 6: bist_fail 7: cm0_sleeping 8: cm0_sleepdeep 9: cm0_sleep_hold_ack_n 10: cm4_sleeping 11: cm4_sleepdeep 12: cm4_sleep_hold_ack_n 13: cm4_power 14: cm4_act_retain_n 15: cm4_act_isolate_n 16: cm4_enabled 17: cm4_reset_n 18: cm4_pwr_done 19: mmio_ram0_ctl1_power[0] (Power control for SRAM0 macro0) 20: mmio_ram0_ctl1_retain_n[0] (Retention control for SRAM0 macro0) 21: mmio_ram0_ctl1_isolate_n[0] (Isolation control for SRAM0 macro0) |
DDFT_OUT1_SEL | Select signal for CPUSS DDFT[0] 0: clk_r of the Main flash (which is clk_hf for SONOS Flash) 1: Flash data output bit ‘0’ (r_q[0]) 2: Flash data output bit ‘32’ (r_q[32]) 3: Flash data output bit ‘64’ (r_q[64]) 4: Flash data output bit ‘127’ (r_q[127]) 5: bist_fm_enabled 6: bist_fail 7: cm0_sleeping 8: cm0_sleepdeep 9: cm0_sleep_hold_ack_n 10: cm4_sleeping 11: cm4_sleepdeep 12: cm4_sleep_hold_ack_n 13: cm4_power 14: cm4_act_retain_n 15: cm4_act_isolate_n 16: cm4_enabled 17: cm4_reset_n 18: cm4_pwr_done 19: mmio_ram0_ctl1_power[0] (Power control for SRAM0 macro0) 20: mmio_ram0_ctl1_retain_n[0] (Retention control for SRAM0 macro0) 21: mmio_ram0_ctl1_isolate_n[0] (Isolation control for SRAM0 macro0) |